# SMIC doubles 7nm capacity to feed Huawei's Ascend ramp, pilots 5nm
> China's lead foundry scales N+2 output for Ascend 910C/910D as Huawei targets ~600k dies; HBM and yields, not lithography, are now the bottleneck

**Meta:** type: story · date: 2026-06-15 · heads: El juego largo, Lo que no dicen · 9 takes · 3 lenses · 5 regions

## Summary

[SMIC](/es/entity/smic) is reportedly doubling its 7nm (N+2) capacity in 2026 to supply [Huawei's](/es/entity/huawei)
[Ascend](/es/entity/smic) AI accelerators, the 910C (53B transistors, N+2) and incoming 910D, while running pilot
lines for a 5nm process via DUV multi-patterning, with mass production targeted this year for [Huawei](/es/entity/huawei)
and Alibaba. Huawei aims for ~600k Ascend 910C dies in 2026 (roughly double prior output), and up to ~1.6M
dies across the line. The constraint has shifted: analysts say [HBM](/es/entity/hbm) and advanced packaging, not
[Smic](/es/entity/smic) logic wafers, now gate the ramp, with Huawei holding die banks waiting on memory. China's
~$47.5B "Big Fund III" underwrites yields estimated at 30-40%, far below [TSMC's](/es/entity/tsmc) 80%+, as a
[sanctions](/es/entity/united-states)-era national-security cost rather than a profit centre.

## By the numbers

- 2x, planned increase in SMIC 7nm (N+2) capacity in 2026.
- ~600k, Huawei Ascend 910C dies targeted for 2026; up to ~1.6M across the Ascend line.
- 53B, transistors on the Ascend 910C (SMIC N+2 process).
- 30-40%, estimated SMIC advanced-node yield (vs TSMC 80%+).
- ~$47.5B, China's "Big Fund III" national semiconductor fund.

## Why it matters

SMIC is China's escape hatch from the AI-chip controls: every Ascend die it ships is one Beijing did not
have to buy from Nvidia or smuggle. Doubling N+2 capacity narrows the gap on volume even as yields stay
poor and EUV stays blocked. But if HBM and packaging are the true chokepoint, the controls bite through
memory and tools, sharpening the stakes of the ASML and HBM-export fights.

## What to watch

- Whether SMIC's 5nm pilot reaches credible mass production this year.
- Huawei's actual Ascend die output vs the ~600k target, and HBM sourcing.
- Any new BIS action on tools/components routed to SMIC (cf. Applied Materials settlement).

## Regional takes (batched by bias / lens)

### unlabelled
- **SemiAnalysis** (United States, en) — Detailed teardown of China's AI-chip production ramp, SMIC N+2 wafer capacity, Ascend die-bank strategy, yields, and the argument that HBM supply, not SMIC lithography, is now the binding constraint.
  Source: https://newsletter.semianalysis.com/p/china-ai-and-semiconductors-rise
- **RCR Wireless** (United States, en) — 
  Source: https://www.rcrwireless.com/20250930/ai-infrastructure/huawei-ai-chips-2
- **SCMP** (Hong Kong, en) — 
  Source: https://www.scmp.com/tech/tech-war/article/3239382/huawei-smic-chip-advances-cannot-be-stopped-futile-us-sanctions-says-tsmc-and-semiconductor-veteran
- **TechInsights** (Canada, en) — 
  Source: https://www.techinsights.com/blog/chinas-smic-plays-7-nm-card
- **wccftech** (Global, en) — 
  Source: https://wccftech.com/china-is-expected-to-significantly-increase-its-ai-chip-production-within-the-upcoming-years/
- **enkiAI** (Global, en) — 
  Source: https://enkiai.com/ai-market-intelligence/smic-ai-chip-strategy-2026-inside-chinas-5nm-power-play/
- **Abhishek Gautam (Hua Hong 7nm)** (India, en) — 
  Source: https://www.abhs.in/blog/hua-hong-7nm-china-second-chipmaker-biren-ai-chips-2026

### hardware/industry desk
- **Tom's Hardware** (United States, en) — Reports SMIC on track for 5nm pilot/mass-production this year for Huawei, achieved via DUV multi-patterning without EUV. Stresses the cost penalty: yields estimated at 30-40% versus TSMC's 80%+, sustained only because Beijing treats advanced logic as national security rather than a profit centre.
  > "SMIC targets 5nm via DUV multi-patterning at an estimated 30-40% yield, viable only because Beijing subsidises it as national security."
  Source: https://www.tomshardware.com/tech-industry/semiconductors/chinas-smic-foundry-on-track-to-produce-5nm-smartphone-chips-for-huawei-this-year-report

### independent semiconductor analysis
- **SemiAnalysis (Ascend ramp)** (United States, en) — Argues the Ascend bottleneck has shifted from SMIC logic wafers to HBM and advanced packaging: Huawei has die banks of Ascend silicon waiting on memory. Notes continued reliance on stockpiled and externally-sourced inputs despite the self-sufficiency narrative.
  > "Huawei's Ascend ramp is gated by HBM and packaging, not SMIC logic, die banks sit waiting on memory."
  Source: https://newsletter.semianalysis.com/p/huawei-ascend-production-ramp

## Across the graph
- Related: [[h200-china-export-standoff]], [[china-rare-earth-controls]], [[asml-euv-china-components-dispute]]
- Entities: Smic, China, Huawei, United States

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Canonical: https://rbtfl.xyz/es/n/smic-7nm-double-ascend-2026