# UALink publishes four specs, formalising the open answer to NVLink
> The 115-member consortium ratifies In-Network Compute, a UCIe 3.0-compliant Chiplet spec, Manageability and a split 200G physical layer, scale-up fabric as an open standard

**Meta:** type: story · date: 2026-04-07 · heads: A mudança silenciosa, O jogo longo · 11 takes · 3 lenses · 3 regions

## Summary

The [UALink Consortium](/pt/entity/ualink), over 115 members, board led by AMD, Apple, AWS, Cisco, Google, HPE, Intel, Meta, Microsoft and Synopsys, ratified four specifications on 7 April 2026, hardening the open scale-up fabric meant to rival Nvidia's proprietary [NVLink](/pt/n/nvlink-fusion-marvell-2026). UALink Common 2.0 adds **In-Network Compute** (computation inside the fabric, chasing NVLink's collective-operation edge); the 200G Data Link/Physical Layers were **split out** so speeds can advance without reopening the protocol; Manageability 1.0 adds gNMI/YANG/Redfish control planes; and **Chiplet 1.0** is fully compliant with the [UCIe 3.0](/pt/entity/ucie) spec, stitching UALink into existing chiplet SoCs. The 1.0 line links up to 1,024 [accelerators](/pt/entity/amd) per pod at 200Gbps per lane; first silicon from AMD, [Intel](/pt/entity/intel) and [Astera Labs](/pt/entity/astera-labs) is due late 2026.

## By the numbers

- 4, specifications ratified 7 April 2026 (Common 2.0, 200G DL/PL 2.0, Manageability 1.0, Chiplet 1.0).
- 115+, UALink member companies.
- 1,024, accelerators linkable per pod under the 200G spec.
- 200 Gbps, per-lane throughput (PHY based on IEEE P802.3dj).
- Late 2026, first UALink hardware (AMD, Intel, Astera Labs).

## Why it matters

Scale-up interconnect is where Nvidia's moat is widest. An open, multi-vendor fabric that hits 1,024-accelerator pods, folds compute into the network, and snaps into UCIe chiplets lets AMD, Intel and the hyperscalers' custom silicon compete on equal fabric terms, or keeps them dependent on NVLink Fusion if it stalls in hardware.

## What to watch

- Whether late-2026 UALink silicon ships on schedule and interoperates across vendors.
- Adoption of In-Network Compute vs Nvidia's SHARP/NVLink collective offload.
- Chiplet 1.0 uptake as the UCIe-compliant die-to-die path for non-Nvidia accelerators.

## Regional takes (batched by bias / lens)

### unlabelled
- **UALink Consortium (Business Wire)** (United States, en) — The consortium's own 7 April 2026 release ratifying four specifications, UALink Common 2.0 (In-Network Compute), 200G DL/PL 2.0, Manageability 1.0 and Chiplet 1.0 (UCIe 3.0-compliant), the primary record for the scope and member list.
  Source: https://www.businesswire.com/news/home/20260407620696/en/Ultra-Accelerator-Link-UALink-Consortium-Publishes-Four-Specifications-Defining-In-Network-Compute-Chiplets-Manageability-and-200G-Performance
- **HPCwire** (United States, en) — 
  Source: https://www.hpcwire.com/off-the-wire/ualink-consortium-publishes-4-specifications-defining-in-network-compute-chiplets-manageability-and-200g-performance/
- **SDxCentral** (United States, en) — 
  Source: https://www.sdxcentral.com/news/ualink-consortium-releases-200g-10-specification-for-ai-accelerator-interconnects/
- **Network World** (United States, en) — 
  Source: https://www.networkworld.com/article/3957541/ualink-releases-inaugural-gpu-interconnect-specification.html
- **StorageReview** (United States, en) — 
  Source: https://www.storagereview.com/news/ualink-consortium-finalizes-1-0-specification-for-ai-accelerator-interconnects
- **Design & Reuse** (France, en) — 
  Source: https://www.design-reuse.com/news/202530342-ultra-accelerator-link-trade-ualink-trade-consortium-publishes-four-specifications-defining-in-network-compute-chiplets-manageability-and-200g-performance/
- **Blocks & Files** (United Kingdom, en) — 
  Source: https://blocksandfiles.com/2025/04/09/the-ultra-accelerator-link-consortium-has-released-its-first-spec/
- **Chiplet Marketplace** (United States, en) — 
  Source: https://chiplet-marketplace.com/insights/news/ualink-specifications-in-network-compute-chiplets-manageability-200g
- **TMCnet** (United States, en) — 
  Source: https://www.tmcnet.com/usubmit/-ultra-accelerator-linktrade-ualinktrade-consortium-publishes-four-specifications-/2026/04/07/10360114.htm

### networking-standards trade desk
- **Converge Digest** (United States, en) — Frames the four-spec drop as UALink moving from a single 1.0 link spec to a layered family, splitting the 200G physical layer off so speeds can advance without reopening the protocol, and reads In-Network Compute as the consortium chasing NVLink's collective-operation advantage for distributed training.
  > "Splitting the DL/PL spec lets UALink add new physical layers and speeds without reopening the protocol, In-Network Compute targets NVLink's collective-ops edge."
  Source: https://convergedigest.com/ualink-2-0-adds-in-network-compute-chiplet-support-and-200g-performance/

### data-centre infrastructure desk
- **DatacenterDynamics** (United Kingdom, en) — Tracks UALink as the open scale-up fabric backed by AMD, Intel, Astera Labs, AWS, Google, Meta and Microsoft, linking up to 1,024 accelerators per pod at 200Gbps per lane, with first silicon expected late 2026, positioned explicitly as the industry's collective answer to Nvidia's proprietary NVLink.
  > "UALink links up to 1,024 accelerators per pod at 200Gbps per lane; first hardware from AMD, Intel and Astera Labs arrives late 2026."
  Source: https://www.datacenterdynamics.com/en/news/ualink-consortium-releases-200g-10-specification-for-ai-accelerator-interconnects/

## Across the graph
- Related: [[arm-agi-server-cpu-2026]], [[nvlink-fusion-marvell-2026]], [[ultra-ethernet-1-0-2026]]
- Entities: Ualink, Ucie, Amd, Intel, Broadcom, Astera Labs, United States

---
Canonical: https://rbtfl.xyz/pt/n/ualink-2-0-specs-2026